It's no secret that power is emerging as the most critical issue in system-on-chip (SoC) design today. In this paper, Common Power Format (CPF) has been used to describe the power distribution and its control at RTL level in a system on chip (SoC) design. With CPF one can model the low power aspect of a design more effectively. The power aware results for an SoC, Voice Modulation Engine (VME) were obtained using Cadence power aware simulation software. It gives the ability to functionally verify the power management techniques at the RTL level, reducing costs significantly both in terms of effort and time.