We propose a framework that can generate all digital PLL (ADPLL) from the design specifications. It uses double loop edge injection type ADPLL[1] with phase interpolation oscillator. A calibration logic to correct errors of two oscillators is introduced based on [1]. Division of the frequency divider and edge injection timing are decided according to the given specification. Input / output frequency and FCW resolution are given as specifications of the PLL in the framework. The generation time are 1 minutes 13 seconds to 1 minutes 38 seconds to generate PLLs with 40MHz input frequency and 170 to 1150MHz output frequencies. Simulation results show that RMS jitters are 3.92 to 13.84ps for output frequencies of 200, 400, 600, 800, and 1000MHz. Compared to existing manual designs of PLL, the proposed framework can generate ADPLLs with comparative performance in much shorter design time.