In this paper, we propose a method to evaluate the impact of a transient fault in CORDIC processors. The proposed approach takes into account the spatial and temporal localization of the fault. It also embeds the probability that such a fault occurs. By defining a fault impact coefficient, it is possible to identify the most critical arithmetic blocks and thus to implement an optimized strategy for fault tolerance. We analyzed two structures of CORDIC processors and we showed how to get a better tradeoff between the penalty (area and delay overhead) and the fault tolerant improvement.