An integrated receiver consisting of RF front ends, analog baseband chain with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm2. The RF front end consists of three parallel signal channels intended for L,C and X-band of the SAR receiver. The baseband (BB) is selectable between 50 MHz and 160 MHz bandwidths through switches. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 dB and 37 dB and noise figure of 11 dB and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz baseband and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz baseband and 8 bit mode ADC.