This paper presents a new approach to estimate the n-sigma chip leakage current in the chip leakage probability density function of statistical leakage analysis (SLA) through gate-level deterministic leakage analysis (DLA). Although SLA provides accurate result than corner-based analysis, it is an impractical solution in recent technology comprising millions logic cells in a system since its computational complexity is O(N2). The proposed method uses DLA, and this makes it not only efficient but also suitable for use in the existing design environments. In addition, by providing the upper and lower bounds of SLA results, n-sigma chip leakage, the proposed method avoids the pessimism of existing DLA methods.