In this paper, we propose two contributions to the simulation and design of an All-Digital Phase-Locked Loop (ADPLL) for RF applications. First, we extend the behavioral model we already proposed, in order to include detailed fractional aspects. Second, we propose a new adaptive algorithm that can be integrated in this ADPLL in order to lower its hardware complexity, and argue on a recently proposed algorithm for DCO gain estimation. These points are illustrated through simulations.