Low-power low-voltage library cells and memories

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 13 Nov 2002Publisher:IEEEJournal:ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)

Authors: Christian Piguet; Jean-Marc Masgonty; Stefan Cserveny; Claude Arm; Pierre-David Pfister;

doi: 10.1109/icecs.2001.957504

Low-power low-voltage library cells and memories

- Summary
- Metrics

Abstract

For future Systems on Chip (SoC) in deep submicron technologies, digital libraries as well as ROM and SRAM memories have to be designed to work at very low supply voltages and to be very robust while considering wire delays, signal input slopes, noise and crosstalk effects. New approaches are presented, such as libraries based on a limited set of standard cells and SRAM with split-bitlines and new asymmetrical RAM cells.

Related Organizations

École Polytechnique Fédérale de Lausanne EPFL
Switzerland

Impact byBIP!

	selected citations These citations are derived from selected sources. This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).	6
	popularity This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.	Average
	influence This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).	Top 10%
	impulse This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.	Average