This paper presents two implementations of the same block turbo decoding algorithm: on the one hand an elementary decoder in association with a sequencer performs the complete turbo decoding process, and on the other hand, the circuit contains one elementary decoder per half-iteration. The choice of different parameters for each algorithm implemented bring the results more or less close to the theoretical limit. First, we briefly describe the iterative process which creates the "turbo" effect and explain the essential choices in order to adapt the algorithm to an ASIC implementation. Then we describe the two prototypes.