Modern digital telecommunication and audio systems include a Digital Phase Locked Loop (D-PLL) in a form of a device or an algorithm. Wireless infrastructure, broadband wire-line networks and high end audio systems require very high performance PLLs. There are several key points required for high performance D-PLL circuits design such as power efficiency, loop bandwidth flexibility and accurate frequency translation. This paper describes a novel D-PLL architecture and presents an analysis of the digital loop filter.