FPGA implementation and verification of LDPC encoder with weight (3, 6) approximate lower triangular matrix

descriptionPublicationkeyboard_double_arrow_right Article 01 Dec 2012Publisher:IEEEJournal:Proceedings of 2012 2nd International Conference on Computer Science and Network Technology

Authors: Yi Hua Chen; Meilin Su; Jheng Shyuan He;

doi: 10.1109/iccsnt.2012.6525993

FPGA implementation and verification of LDPC encoder with weight (3, 6) approximate lower triangular matrix

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Abstract

Compared with general linear block code encoding, LDPC encoding with lower triangular check matrix and approximate lower triangular check matrix carry out encoding directly by parity check matrix H. This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed introduction to the encoding mechanism of the approximate lower triangular LDPC, and completed the implementation and hardware verification of FPGA SDR system.

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Oriental Institute of Technology
Taiwan

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