PEAS-III: an ASIP design environment

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 07 Nov 2002Publisher:IEEE Comput. SocJournal:Proceedings 2000 International Conference on Computer Design

Authors: Makiko Itoh; Shigeaki Higaki; Yoshinori Takeuchi; Akira Kitajima; Masaharu Imai; Jun Sato; Akichika Shiomi;

doi: 10.1109/iccd.2000.878319

PEAS-III: an ASIP design environment

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Abstract

In this paper, an architectural level processor design environment PEAS-III is proposed. Pipelined processors designed by this system can include multi-cycle operation, delayed branch and external interrupt. The data path and control logic of the processor are generated from the clock based micro-operation description of instructions. The ease of large design space exploration through experiments using several subsets of MIPS R3000 instruction set.

Related Organizations

National Institute of Technology, Tsuruoka College
Japan
Osaka University
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National Institute Of Technology
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Shizuoka University
Japan

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