The VLSI design of a one-chip vector processor (VP) for parallel digital signal processing (DSP) systems is described. The VP aims at a peak performance of 100 MFLOPS (32-b) for typical digital signal processing applications. To achieve this performance based on existing CMOS technology, a very-long-instruction-word-type pipeline architecture was used. The pipeline processing architecture and the functional units configuration are shown. A high-level behavioral-description-based CAD system called PARTHENON was used to design the functions and logic circuits of VP. The suitability and effectiveness of PARTHENON for the VP design are shown in terms of parallel operation and pipeline-stage description. The estimated work load in the VP design with PARTHENON is one order of magnitude smaller compared to conventional CAD tools. >