Network on Chip architecture for BP neural network

null Yiping Dong; null Takahiro Watanabe

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https://doi.org/10.1109/icccas...

Article . 2008 . Peer-reviewed

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Network on Chip architecture for BP neural network

descriptionPublicationkeyboard_double_arrow_right Article 01 May 2008Publisher:IEEEJournal:2008 International Conference on Communications, Circuits and Systems

Authors: null Yiping Dong; null Takahiro Watanabe;

doi: 10.1109/icccas.2008.4657930

Network on Chip architecture for BP neural network

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Abstract

Recently, networks-on-chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of artificial neural networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (back-propagation) and evaluated by network-on-chips. Experimental results show that for has a great reduction in communication load and a high connection per second (CPS) compared with traditional BP-ANNs. It is also reconfigurable, expandable and stable to meet various problems.

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Waseda University
Japan

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