Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to Ceff and RC - ?are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.