UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 400 Mbps in full specification mode and 200 Mbps in mandatory mode. To implement this high speed, it needs clock speed about several hundreds, it has some implementation bottle neck such as Viterbi decoder. In this paper, we analyze the requirements of Viterbi decoder for UWB system, and suggest appropriate architecture for 200 Mbps mandatory mode that could be implemented by ASIC. Using this architecture, we show the results that simulate optimum soft-input bit width and trace-back length. At last, we show hardware implementation results of Viterbi decoder for 200 Mbps mandatory mode