This paper presents an architecture for the All Digital Phase Locked Loop (ADPLL) suitable for low frequency applications having an optimum area and power overhead. The described ADPLL consists of Phase Frequency Detector (PFD), Binary search module, Digital Controlled Oscillator (DCO) and Direct Digital Synthesizer (DDS) all of these blocks are realized as digital and discrete-time components. To calculate the delay line length which corresponds to the appropriate output frequency of the DCO a binary search algorithm is used. The binary search algorithm facilitates fast locking for arbitrary frequency changes. The delay line length is also used as a Frequency Tuning Word (FTW) to tune the output sine and cosine signal frequency generated by the DDS. The DDS employs a Coordinate Rotational Digital Computer (CORDIC) algorithm instead of an Look Up Table (LUT) for phase to amplitude conversion thereby reducing the area overhead. The proposed ADPLL is implemented using Verilog HDL, simulated using Mentor Graphics Questa-sim tool and synthesized using Cadence EDA tool at 45 nm technology. The DCO in the proposed design has a period jitter measured to be 7.84 ps which shows an improvement of 65% over the referred paper. The proposed ADPLL can lock up-to a maximum frequency of 200 MHz.