Summary form only given. At a point in time when it is harder to harvest more instruction-level parallelism and to push the clock frequency to higher levels, industry has opted for integrating multiple processor cores on a chip. It is an attractive way of reducing the verification time by simply replicating moderately complex cores on a chip, but it introduces several challenges. The first challenge is to transform the processing power of multiple cores to a high application performance. The second challenge is to bridge the increasing speedgap between processor and memory by more elaborate on-chip memory hierarchies. Related to the second challenge is how to make more effective use of the limited bandwidth out of and into the chip. A third cross-cutting challenge is how we can move forward and yet manage the complexity of billion transistor chips. In this paper the author elaborates on the opportunities that chip-multiprocessing offer along with the research issues that it introduces. Even if multiprocessing has been studied for more than two decades, the tight integration of cores and their on-chip memory subsystems opens up new unexplored terrains. The author discusses and reflects upon approaches to explore new forms of parallelism as well as approaches to manage the on-chip cache hierarchies in the pursuit of making multi-core chips deliver higher performance.