A pipeline parallel architecture for a fuzzy inference processor

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 07 Nov 2002 Italy Publisher:IEEEJournal:Ninth IEEE International Conference on Fuzzy Systems. FUZZ- IEEE 2000 (Cat. No.00CH37063), volume 1, pages 257-262

Authors: ASCIA, Giuseppe; CATANIA, Vincenzo;

doi: 10.1109/fuzzy.2000.838668

handle: 20.500.11769/89290

A pipeline parallel architecture for a fuzzy inference processor

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Abstract

The paper presents the architecture of a VLSI processor for applications based on fuzzy logic. The main features of the architecture are: a pre-computation phase of the positive degree of truth of the antecedent with fuzzy inputs; a detection phase of the rules positive degree of activation, parallelism in some phases of inference which is split into a sequence of pipeline stages. The processing speed is up to 16.7 MFLIPS for inferences with 64 rules with 4 linguistic variables.

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Italy

Related Organizations

University of Catania
Italy

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