Protocol transducer synthesis is one of the most significant issues for efficient IP core reuse in SoC design. The authors proposed automatic protocol transducer synthesis method (Watanabe et al., 2006), (Ishikawa et al., 2006). In this paper, an application of the protocol synthesis method to reconfigurable architecture on FPGA was proposed that enable to utilize various IPs dynamically. In coarsegrained reconfigurable architectures such as hardware OS, protocol transducers should be also dynamically reconfigured to make the dynamically loaded IPs able to communicate with each other. Our basic approach is division of a protocol transducer into partial ones. A whole transducer is constructed from these partial transducers by simply putting them side by side physically. Each partial transducer can be given in either layout design hard macro or in netlist