An architecture for asynchronous FPGAs
Wong, Catherine G.; Martin, Alain J.; Thomas, Peter;
An architecture for asynchronous FPGAs
We present an architecture for a quasi delay-insensitive asynchronous field-programmable gate array. The logic cell is a complete asynchronous pipeline stage and the interconnects are entirely delay insensitive, eliminating all timing issues from the place-and-route procedure.
Submitted - afpga-030808.ps
United States
- California Institute of Technology United States
asynchronous vlsi, fpga, asynchronous vlsi, fpga, 004
asynchronous vlsi, fpga, asynchronous vlsi, fpga, 004
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These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
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This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
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