Sliding block Viterbi decoders in FPGA

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 01 Aug 2012Publisher:IEEEJournal:22nd International Conference on Field Programmable Logic and Applications (FPL)

Authors: Mário P. Véstias; Horácio C. Neto; Helena Sarmento;

doi: 10.1109/fpl.2012.6339215

Sliding block Viterbi decoders in FPGA

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Abstract

In this paper, we analyze the design of sliding block Viterbi decoders in FPGA based on two proposed parallel Viterbi decoders with different area/performance ratios. Viterbi decoders for two wireless technologies were designed considering the proposed Viterbi decoders achieving reductions in resource utilizations of more than 50% compared to other state-of-the-art proposals1.

Related Organizations

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento
Portugal

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