This work presents an Embedded Routing Database (ERDB), which contains the complete description of the inter-tile routing shapes available in various Xilinx FPGA tiles, and the mapping of Programmable Interconnection Point (PIP) bits within the FPGA configuration bit stream. ERDB provides the RC system with knowledge of its own architecture and facilitates RC systems in implementing autonomic (self-managing and adaptive) computing. ERDB also protects the integrity of the RC system and supports design Intellectual Property (IP) protection. The paper describes the automated generation of a size-optimised ERDB (3.7 MB memory footprint for the Virtex-5 LX50T device) and its application within the Secure Reconfiguration Controller (SeReCon), as a minimised FPGA fabric description for on-line verification of IP core's integrity during partial reconfiguration. Results demonstrate the feasibility and accuracy of the SeReCon/ERDB-based design (IP core) routing verification that, when applied to an example IP block, detects >99% of the configured PIPs.