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Configurable architecture for memory BIST

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 01 Sep 2011Publisher:IEEEJournal:2011 9th East-West Design & Test Symposium (EWDTS)
Authors: Atieh Lotfi; Parisa Kabiri; Zainalabedin Navabi;

doi: 10.1109/ewdts.2011.6116571

Configurable architecture for memory BIST

Abstract

The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
2
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