We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows −39% mobility for 170nm narrow 2µm long channel, but +21% Ieff at Lg=20nm and gate-to-STI distance of 59nm. It is translated into a −15% delay reduction for ring oscillators of 1-finger inverters. Layout dependences are explained by physical strain measurements and reproduced by a stress-based electrical model.