
handle: 11311/1002924
This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity. It will be also demonstrated that this property can be generalized to the case of PLLs based on coarse time-to-digital converters with mid-rise quantization, whose adoption speeds up lock transients. The results are assessed in a fabricated 3.6-GHz fractional-N digital phase-locked loop.
sezele, PLL, CMOS, Wireless, Quantisation, IC
sezele, PLL, CMOS, Wireless, Quantisation, IC
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