vfTLP characteristics of ESD devices in Si gate-all-around (GAA) nanowires

descriptionPublicationkeyboard_double_arrow_right Article 01 Sep 2016Publisher:IEEEJournal:2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

Authors: Shih-Hung Chen; Dimitri Linten; Geert Hellings; Anabela Veloso; Mirko Scholz; Roman Boschke; Guido Groeseneken; +3 Authors

doi: 10.1109/eosesd.2016.7592555

vfTLP characteristics of ESD devices in Si gate-all-around (GAA) nanowires

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Abstract

Beyond 7nm nodes, gate-all-around (GAA) nanowire (NW) is a promising device architecture. However, new architecture can result in intrinsic ESD performance degradation. In this work, we study vfTLP characteristics of GAA ESD devices. Transient analysis bring an in-depth understanding on physical failure mechanism of GAA devices during CDM ESD events.

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Katholieke Universiteit Leuven
Belgium

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