We demonstrate a novel method for protection of the power supplies on a low-power microprocessor. The protection method splits the I/O supply bus into two segments, relying on the voltage difference between the supplies to distinguish between an ESD event and normal operation. We examine the effects of supply clamp placement in the die using SPICE. Under certain circumstances, parasitic coupling, not representative of real-world ESD, in the HBM tester has a strong influence on this method's ESD performance. The origin of the parasitics and their defeat are thoroughly investigated. With tester parasitics removed, the ESD circuits meet their expected performance.