Medium voltage multi-level inverters: Hardware-in-the-loop (HIL) simulations
Medium voltage multi-level inverters: Hardware-in-the-loop (HIL) simulations
This paper presents low cost flexible FPGA based HIL simulator and HIL simulation results for 5, 9, and 13-level topologies of medium voltage multi-level inverters that controlled by carrier based pulse-width-modulation (PWM) algorithm. The applications of these inverters can be synchronous or induction motors. The HIL simulation results for each topology are introduced and compared to the conventional simulation results in concept of the load current total harmonic distortion (THD). In addition, the influence of control parameters such as frequency modulation ration, amplitude modulation ration and phase shift between carrier and modulation signals on the load current THD in the HIL simulator is analyzed, and the optimal parameters are introduced.
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