Register protection against soft errors remains a major concern for deep sub-micron systems due to technology scaling. Error Correction Codes (ECCs) improve protection at the price of data redundancy. Reducing such redundancy is of upmost importance for memories, although it is less important in registers. A major requirement for register protection is to keep codes' encoding and decoding latencies as short as possible. Ultrafast Single Error Correction codes are an interesting option for this purpose. They allow very low encoding/decoding delays, but at the cost of a high redundancy. This paper proposes a new method to develop Ultrafast codes, adding new error coverages. Different Ultrafast codes have been designed, simulated and compared to other codes. Using Ultrafast codes, double error detection or, alternatively, double adjacent error correction can be achieved using 2-gate-delay encoding and 4-gate-delay decoding circuits. One of the major advantages of Ultrafast codes is that these delays do not depend on the register length.