Through-silicon-via (TSV) approach has been widely investigated recently for three-dimensional (3D) electronic packaging integration. TSV wafer warpage is one of the most challenges for successfully subsequent processes. In this work, wafer level warpage modeling methodology has been developed by finite element analysis (FEA) method using equivalent material model. The developed modeling methodology has been verified by numerical results and experiment data. With using the developed model, wafer warpage has been simulated and analyzed by considering different factors such as annealing temperature, Cu overburden thickness, TSV depth and diameter. Simulation results show that wafer warpage increases with increasing annealing temperature and increasing Cu overburden thickness. Such findings have been successfully used in the TSV process optimization to reduce wafer warpage after annealing process. Submodeling methodology has also been developed to determine wafer stress accurately. Wafer bending stress is larger at wafer surface and close to the TSV edge. Bending stress is higher at the edge of TSV with finer pitch.