High performance logic ICs are rapidly migrating from peripheral bonded package configurations to area array, flip chip configurations. Total die I/O is exploding from <800 pins to more than 3500 pins with little abatement in the rate of increase in total silicon area. Traditional flip chip package substrate technologies, such as co-fired ceramic, are not able to adequately support this growing industry trend due to inherent limitations in thermal cycling reliability of the level 2 interface, density, electrical performance, and cost of use. A new, cost effective, organic flip chip package substrate technology has been developed, prototyped, qualified, and is being ramped into production. This laminated technology uses a nonwoven polytetrafluoroethylene (PTFE) composite dielectric combined with a fabrication technology that has produced the highest density organic substrates yet disclosed. The technology has been used to fabricate packages for die up to 18.5 mm by 18.5 mm with more than 3800 total I/O. Body sizes of up to 45 mm have been fabricated. In this paper, we will discuss the materials of construction, process technology, reliability characterization, thermo-mechanical characterization, and electrical performance of various cross-sections using this new technology.