Chip scale packaging for memory devices

descriptionPublicationkeyboard_double_arrow_right Article 27 Nov 2002Publisher:IEEEJournal:1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)

Authors: Y. Akiyama; A. Nishimura; I. Anjoh;

doi: 10.1109/ectc.1998.678737

Chip scale packaging for memory devices

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Abstract

A low cost, high reliability chip scale package has been developed for memory devices. The developed CSP can be applied to center pad type devices such as DRAM and to peripheral pad type devices such as SRAM and Flash. Reliability and high volume productivity are the main technological challenges that have to be overcome for chip scale packaging. This paper unveils Hitachi's original CSP concept and shows how our CSP overcomes these challenges.

Related Organizations

Hitachi (Japan)
Japan

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