To overcome CMOS challenges including leakage power, volatility, scalability, and soft error vulnerability, Spin Transfer Torque Random Access Memory (STT-RAM) as a non-volatile memory has been utilized. Write error occurring because of variation in the fabrication process is one of the disadvantages of STT-RAM just like other devices. Given the fact that different current densities are required to write '1' and '0', in this paper, two different methods based on modification in write circuit are proposed: 1) dual source write circuit is proposed to decrease parallel write energy that leads to a noticeable decrement in power consumption, 2) the threshold voltage of active transistors in anti-parallel writing process is decreased to raise the temperature of the memory cell. This increment in Magnetic Tunneling Junction (MTJ) temperature leads to Write Error Rate (WER) reduction. In order to validate our results, functional simulations are performed and compared with the related works. Results approved power gain, performance improvement, and WER reduction by optimizing VDD and Vth values. We achieve 11.38% decrement in overall write time without any area or total power overhead.