The {2^n + 1, 2^n - 1, 2^(2n+1) - 3, 2^(2n) - 2} moduli set and the respective reverse converter have been recently proposed for supporting Residue Number Systems (RNSs). The reverse converter originally proposed was based on the Chinese Remainder Theorems (CRTs), in particular the commonly called new CRTs, and requires at the end a 6nbit carry propagate adder to compute the binary value. In this paper we propose a more efficient Very-Large-Scale Integration (VLSI) reverse converter for the referred moduli set following a similar approach based on the Mixed-Radix Conversion (MRC). Experimental results show a reduction in the conversion delay of 22% and 17% without impact in the circuit area regarding the related art for a 90 nm ASIC and FPGA technology, respectively.