This paper describes the on-chip SRAMs design flow in one SOC chip. We show a model to estimate the coupling noise in the existence of power rings around SRAMs. SRAM blocks usually use the lower level metals and the top metals over the SRAM could be used for power distribution and global signals. Power noise has the global impact on SRAMs and chip performance. We discuss the full chip power grid planning methodology, including power rings and power strap lines over SRAM blocks, in order to meet the power noise budget.