Nonvolatile repair caches require less area than traditional row, column, or block redundancy schemes, to repair random defective memory cells in deep submicron embedded SRAMs and new nonvolatile memories such as FeRAM, MRAM, and OUM. Small memories with few defects can be repaired efficiently in real time by the direct mapped nonvolatile repair cache whereas large memories with many defects can be repaired more effectively and in real time by the N way set associative repair cache. An 8 way set associative repair cache was implemented in the Texas Instruments-Agilent Technologies 64 Mbit FeRAM chip.