Analyzing BIST robustness

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 13 Nov 2002Publisher:IEEE Comput. SocJournal:Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Authors: Janusz Sosnowski;

doi: 10.1109/dftvs.2001.966758

Analyzing BIST robustness

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Abstract

Deals with the problem of fault detection and fault handling robustness in BIST schemes. In particular we analyze the susceptibility of signature analyzers to internal faults. Various fault models (black box) within the analyzer circuitry are taken into account. Moreover we check fault impact on software procedures related to BIST and error handling mechanisms using software implemented fault injector.

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