Fault-tolerant processors and processing architectures traditionally have relied on higher level (module level and above) techniques for fault detection and recovery. The advent of VLSI and VHSIC technology, with increasing numbers of gates on a chip and increasing numbers of I/O pins available, has provided increasing opportunities for the inclusion of on-chip fault and defect tolerance. On-chip fault tolerance, encompassing hardware concurrent error detection and recovery mechanisms, offers the potential for improving system availability and supporting real-time fault tolerance. This paper describes the successful development and demonstration of a Laser Fault Injection (LFI) technique to inject soft, i.e., transient faults into VLSI circuits in a precisely-controlled, non-destructive, non-intrusive manner for the purpose of validating fault tolerant design and performance. This technique, as well as enabling the validation of fault-tolerant VLSI designs, also offers the potential for performing automated testing of board-level and system-level fault tolerant designs including the operating system and application software. It requires no vacuum test chamber, radioactive source, or additional on-chip fault injection circuitry. The laser fault injection technique has the advantage that it supports in situ testing of circuits and systems operating at speed. It can also emulate transient error conditions that standard diagnostic test patterns and techniques may miss.