In-place Polarity inVersion (IPV) has been proposed to mitigate the single event upset (SEU) induced soft errors for academic VPR FPGA architectures, and this paper extends the original IPV so that it can be used for commercial FPGA architectures. Different from the original IPV, we use a new soft error model based on signal probability and propose a simple yet effective greedy based algorithm. To validate the effectiveness of IPV 2.0, we map circuits by ISE followed by IPV 2.0 to a Xilinx Virtex-5 x5vlx110t FPGA, and inject faults to the mapped circuits during run time. Experiments show that IPV 2.0 reduces soft errors by about 1.4× on average and up to 2× when compared to the circuits mapped by ISE without IPV 2.0.