Low-power devices are indispensable for modern electronic applications, and numerous hardware/software techniques have been developed for drastically reducing functional power dissipation. However, the testing of such low-power devices has increasingly become a serious problem, especially in at-speed scan testing where a transition is launched at the output of a flip-flop and the corresponding circuit response is captured by a flip-flop with a functional clock pulse. The reason is that most or all of the functional constraints with respect to circuit operations and clocking are ignored in at-speed scan testing, which may make test power several times higher than functional power. Excessive test power may cause die/package damage due to excessive heat as well as undue yield loss due to excessive power supply noise, as illustrated in Figure 1. Therefore, it has become imperative to apply low-power testing to low-power devices. In other words, low-power devices cannot be successfully realized without effective and efficient low-power test solutions. This presentation first describes the basics of power dissipation in CMOS circuits. It goes on to highlight the difference between power dissipation in function mode and power dissipation in test mode, and lists the reasons why test power can be several times higher than functional power for low-power device. This presentation then describes the widely used clocking scheme used in at-speed scan testing, namely launch-on-capture (LOC), and shows the different characteristics of shift power and capture power in LOC-based at-speed scan testing. Based on that, a general low-power testing strategy is outlined, featuring the use of design-for-test (DFT) techniques for shift power reduction and the use of test data manipulation techniques for capture power reduction. This presentation then provides a comprehensive review of the state-of-the-art techniques for reducing test (shift or capture) power. Finally, future directions in the research and development of more advanced and sophisticated low-power testing are discussed.