Summary form only given..Advances have been been made recently in assembling nanoscale devices without using photolithography. This important development, which offers the potential for greatly increasing the density of memory cells and logic gates, introduces a new model of computation and new analytical challenges. In this talk we provide an introduction to this new area. The difficulty of assembling irregularly placed nanoscale devices has caused the research community to focus on the crossbar. All known methods for controlling individual nanowires (NWs) in a crossbar by mesoscale wires (MWs) introduces randomness in the connections. This introduces several questions. First, which methods of controlling NWs with MWs devotes the smallest amount of area for this purpose? Second, how can stochastically assembled chips be configured after assembly? Third, since errors will occur during assembly, how can chips be designed to minimize the effect of such errors? Finally, what computational limitations do stochastically assembled, crossbar-based computers introduce? We will address these and other questions.