Ensuring the functional correctness of a SoC is essential for successful design projects. A proven and effective method from Freescale Semiconductor Australia is to employ software application testing at the pre-silicon simulation stage. This method was formalized and implemented into a Software Application Level Verification Methodology (SALVEM). However, despite its successes, SALVEM lacks an effective coverage technique. Existing coverage methods are unsuitable because they do not provide any useful information about the functional applications verified. The contribution of this paper is a coverage method that determines what functional SoC behaviours were tested, and quantifies this information into a coverage metric to estimate the comprehensiveness of SALVEM testing. The paper will outline the coverage method, and explain the abstraction and coverage modelling graph techniques adapted from the formal verification domain of Symbolic Trajectory Evaluation. The coverage method was applied to the Nios SoC and experimental coverage results will be discussed.