The on-going down-scaling of devices in microelectronics has resulted both in reliability problems and in problems regarding power dissipation. Even worse, reducing supply voltages below 1 V has resulted in problems due to inevitable parameter variations from production on one side and from parameter shifts by aging effects on the other hand. So far, much work has been invested in new methods of fault-tolerant computing using code based error detection and -- correction or triple modular redundancy (TMR) at substantial extra cost in hardware and power. On the other hand, there has been a line of development to handle parameter variations by selectively correcting delay faults in order to achieve stable circuit operation and supply voltages down to 0.6V or below. The Razor and Bubble Razor architectures developed for such purpose may even handle short transient faults. However, they are acceptable in terms of overhead only if applied to a small share of signals that suffer from critical paths in combinational logic. What is missing is an architecture that can handle such path delays and transient fault effects at reasonable cost, optionally in combination with methods that allow for the detection and compensation of permanent faults also. The paper presented here shows an effort in this direction and estimates cost and overhead.