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handle: 2117/132753
This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct transformations including conversion to a synchronous elastic form, early evaluation, inserting empty buffers, anti-tokens, and retiming. The design exploration is done by solving an optimization problem followed by simulation of solutions. The method is explained on a DLX microprocessor example. The impact of different microarchitectural parameters on the performance is analyzed.
Peer Reviewed
Delay, Computers, Pipeline, Space exploration, Design optimization, Counting circuits, Wires, Microprocessors -- Design and construction, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Pipeline processing, Design automation, Microarchitecture, Microprocessadors -- Disseny i construcció, Protocols, Clocks
Delay, Computers, Pipeline, Space exploration, Design optimization, Counting circuits, Wires, Microprocessors -- Design and construction, Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Pipeline processing, Design automation, Microarchitecture, Microprocessadors -- Disseny i construcció, Protocols, Clocks
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