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Verification Testing

Name: Verification Testing
Creator: Edward J. McCluskey
Keywords: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

descriptionPublicationkeyboard_double_arrow_right Article 01 Jan 1982Publisher:IEEEJournal:19th Design Automation Conference

Authors: Edward J. McCluskey;

doi: 10.1109/dac.1982.1585544 , 10.1145/800263.809250 , 10.5555/800263.809250

Verification Testing

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Abstract

A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present-day automatic test pattern generation (ATPG) programs. Fault simulation is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher - all irredundant multiple as well as single stuck faults are detected. Test length is easily controlled. The test patterns are easily generated algorithmically either by program or hardware.

Related Organizations

Stanford University
United States

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	impulse This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.	Top 10%

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Fields of Science

engineering and technology

electrical engineering, electronic engineering, information engineering

Fields of Science

engineering and technology

electrical engineering, electronic engineering, information engineering

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