Microarchitecture of HaL's CPU

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 19 Nov 2002Publisher:IEEE Comput. Soc. PressJournal:Digest of Papers. COMPCON'95. Technologies for the Information Superhighway

Authors: Niteen Patkar; Akira Katsuno; Simon Li; Tak Maruyama; Sunil Savkar; Mike Simone; Gene Shen; +2 Authors

doi: 10.1109/cmpcon.1995.512394

Microarchitecture of HaL's CPU

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Abstract

The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level of reliability than is currently available in desktop computers for the commercial marketplace.

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