VHDL as a modeling-for-testability tool

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 04 Dec 2002Publisher:IEEE Comput. SocJournal:Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage

Authors: Alexander Miczo;

doi: 10.1109/cmpcon.1990.63716

VHDL as a modeling-for-testability tool

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Abstract

A number of design methodologies have emerged in recent years to facilitate the testing of digital circuits. These methodologies advocate the use of additional circuitry to enhance controllability and observability of internal circuit nodes. The author takes a slightly different approach to testing by examining the impact of information on the test problem. VHDL circuit descriptions are used. >

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