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An instruction set architecture for the 1990s: parallel and retargetable

Authors: C. Thomson;

An instruction set architecture for the 1990s: parallel and retargetable

Abstract

The G ISA has proved its retargetability by being implemented on three disparate hardware platforms. The first implementation was on a platform with software address translation and floating point; later versions incorporated these features in hardware. The SPS-1 and SPS-2 have distributed memory and use message passing. The PPWB (a Sun 3 workstation with simulated parallelism) uses memory buffers and files to store task memory images. Future implementations could use shared memory, or a combination of shared memory and message passing. Performance on the SPS-2 was dominated by software address translation. However, on the SPS-2 and the PPWB, program performance has approached that of a native implementation. Comparing C and Fortran programs compiled using Myrias software and Sun software shows a low cost increase for G, with beta-release compilers. There is every reason to expect that the delivered translator will match or exceed the performance of existing commercial compilers. >

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citations
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
0
Average
Average
Average
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