The high performance of the Motorola 88000 architecture, which uses ECL (emitter-coupled logic) technology, is discussed. The ECL 88000 is implemented using Motorola's MCA4 technology. This provides about 50000 ECL gates in a macro cell array structure. The ECL 88000 uses both standard and custom macros within the array. The chip is packaged in a TAB (tape automated bonding) package and dissipates about 40 W. The ECL 88000 can be cooled with forced ambient room air. The cache and associated tag stores are implemented with discrete RAMs. The ECL 88000 is 100% object code-compatible with the original CMOS implementation. Software can be transported freely between the two machines. The basic Harvard architecture of the original implementation is maintained. >