Semiconductor industry has been putting tremendous efforts on 2.5D technology in accordance with the increasing demand for better capacity and system performance. This technology enables several dies to communicate up to the speed of Gigabits per second while reducing the cost for a system with heterogeneous components. However, such new technology also poses great challenges whereby the manufacturing of this interconnect structure is a complicated and defect-prone process. Therefore, the success of 2.5D is greatly dependent on Design for Testability (DFT) to ensure excellence in product quality and reliability as well as keeping the yield loss and overall cost low. This paper focuses on Intel's patented, state-of the-art Embedded Multi-die Interconnect Bridge (EMIB) test methodology that can be adopted by 2.5D FPGA/transceiver product. This fault testing methodology is tailored for the post-bond testing based on extension to the IEEE1149.1 Standard together with Automated Test Pattern Generator (ATPG) methodology. The test is able to detect physical defects in the EMIB, such as missing micro-bumps or misalignments between dies, micro-bumps and the interconnect bridge. However, in complex nanometer design nowadays, defects not only can arise during the process of die bonding and assembly, process variation is found to be one of the main contribution to defects as well. Therefore, in order to ensure maximum test coverage on EMIB, stuck-at test and at-speed test is conducted to target different kind of defects including shorts, opens and delay faults. This test methodology is proven reliable with the simulation results showing that various defects can be detected and diagnosed effectively using the proposed methods.